sg2002_trm_cn_v1.02.pdf--章节8.4.2 分数倍频 PLL里分数PLL配置表不对，请帮忙确认。 #103

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opened 2025-09-17 06:20:48 -04:00 by skylark100 · 1 comment

skylark100 commented

2025-09-17 06:20:48 -04:00

(Migrated from github.com)

ssc_syn_set = ssc_freq_indiv_sel2^26/PLL_VCO 这里ssc_freq_in应该是900M，不是1200M.

如下，ssc_syn_set设为610080582，即0x245D1746, 计算：900M/99M * 2^26 =610080582 = 0x245D1746

uint32_t pll_syn_set[] = {
	614400000, // set apll synthesizer  98.304 M
	610080582, // set disp synthesizer  99 M 
	610080582, // set cam0 synthesizer  99 M
	586388132, // set cam1 synthesizer  103 M
};

uint32_t pll_csr[] = {
	0x00208201, // set apll *16/2 (786.432 MHz)
	0x00188101, // set disp *12/1 (1188 MHz)
	0x00308201, // set cam0 *24/2 (1188 MHz)
	0x00148101, // set cam1 *10/1 (1030 MHz)
};

ssc_syn_set = ssc_freq_in*div_sel*2^26/PLL_VCO 这里ssc_freq_in应该是900M，不是1200M. 如下，ssc_syn_set设为610080582，即0x245D1746, 计算：900M/99M * 2^26 =610080582 = 0x245D1746 uint32_t pll_syn_set[] = { 614400000, // set apll synthesizer 98.304 M 610080582, // set disp synthesizer 99 M 610080582, // set cam0 synthesizer 99 M 586388132, // set cam1 synthesizer 103 M }; uint32_t pll_csr[] = { 0x00208201, // set apll *16/2 (786.432 MHz) 0x00188101, // set disp *12/1 (1188 MHz) 0x00308201, // set cam0 *24/2 (1188 MHz) 0x00148101, // set cam1 *10/1 (1030 MHz) };

skylark100 commented

2025-09-17 06:21:19 -04:00

(Migrated from github.com)